1. Field of the Invention
The present invention relates to solid-state image sensing devices, methods for fabricating solid state image sensing devices and a pattern recognition system using the same.
2. Description of Related Art
Integrated circuit image sensors are finding applications in a wide variety of fields, including machine vision, robotics, guidance and navigation, automotive applications, and consumer products such as digital camera and video recorders. Imaging circuits typically include a two dimensional array of photo sensors. Each photo sensor includes one picture element (pixel) of the image. Light energy emitted or reflected from an object impinges upon the array of photo sensors. The light energy is converted by the photo sensors to an electrical signal. Imaging circuitry scans the individual photo sensors to readout the electrical signals. The electrical signals of the image are processed by external circuitry for subsequent display.
Modern metal oxide semiconductor (MOS) design and processing techniques have been developed that provide for the capture of light as charge and the transporting of that charge within active pixel sensors and other structures so as to be accomplished with almost perfect efficiency and accuracy.
One class of solid-state image sensors includes an array of active pixel sensors (APS). An APS is a light sensing device with sensing circuitry inside each pixel. Each active pixel sensor includes a sensing element formed in a semiconductor substrate and capable of converting photons of light into electronic signals. As the photons of light strike the surface of a photoactive region of the solid-state image sensors, free charge carriers are generated and collected. Once collected the charge carriers, often referred to as a charge packets or photoelectrons, are transferred to output circuitry for processing.
An active pixel sensor also includes one or more active transistors within the pixel itself. The active transistors amplify and buffer the signals generated by the light sensing element to convert the photoelectron to an electronic signal prior to transferring the signal to a common conductor that conducts the signals to an output node.
Active pixel sensor devices are fabricated using processes that are consistent with complementary metal oxide semiconductor (CMOS) processes. Using standard CMOS processes allows many signal processing functions and operation controls to be integrated with an array of active pixel sensors on a single integrated circuit chip.
Refer now to FIG. 1 for a more detailed discussion of a photogate active pixel image sensor of the prior art. A substrate 5 heavily doped with a P-type impurity has its surface further doped with a complementary impurity to create a lightly doped P-type epitaxial layer 10. A P-type material is diffused into the surface of the substrate 5 to form the contact diffusions 12 for the P-type epitaxial layer 10. An N-type material is heavily diffused into the surface of the substrate 5 to form the N+ source/drain regions 20 and 40 and the floating diffusion 35. A gate insulator or thin oxide 95 is placed on the surface of the substrate 5 and polycrystalline silicon is formed on the surface to form the photogate 45 and the gates 25 and 35. The N+ source/drain region 20, the floating diffusion 35, and the gate 25 are a transfer gate switch and the floating diffusion 35, the N+ source/drain regions 40, and the gate 35 form the reset gate switch of the active pixel sensor.
The photogate 45 is connected to a photogate biasing signal PG 50. The gate 25 of the transfer gate switch is connected to a transfer gating signals T_GT 65 and the gate 35 of the reset gate switch is connected to the pixel reset signal PIX_RST 70. The N+ source/drain region 40 is connected to a power supply voltage source VDD. The floating diffusion 30 is connected to the gate of the CMOS transistor 85. The drain of the CMOS transistor 85 is connected to the power supply voltage source VDD and the emitter of the CMOS transistor 85 is connected to the drain of the CMOS transistor 80. The gate of the CMOS transistor 80 is connected to the row select signal 75. The CMOS transistor 85 acts as a source follower to buffer the electrical signal created by the photoelectron charge collected in the floating diffusion 30.
When the photogate 45 is activated to a voltage of approximately 4.0V, the hole majority carriers within the p-type epitaxial layer 10 are depleted in the region beneath the photogate 45 to form the depletion layer 55. The photons that impinge upon the photogate 45 are converted to photoelectrons and collected in the depletion layer 55. At the completion of an integration of the collection of the photoelectrons, the transfer gate 25 is activated to turn on the transfer gate switch to transfer the collected photoelectrons to the storage node of the floating diffusion 30. When the collected photoelectrons are retained at the floating diffusion 30 the row select signal is activated to turn on the transistor 80 to gate the pixel output electrical signal PIX_OUT 90 to external circuitry for processing and display. The amplitude of pixel output electrical signal PIX_OUT 90 is indicative of the intensity of the light energy hν or the number of photons 60 absorbed by the photogate 45. Once the pixel output electrical signal PIX_OUT 90 is read out the pixel reset signal is activated to turn on the reset gate switch and the depletion layer 55 and the storage node 30 are emptied of the photoelectrons.
As structured, some of the light energy hν 60 impinges upon the transfer gate switch and the reset gate switch and are converted to stray photoelectrons that collect in the floating diffusion 30. Some of the photoelectrons 62 may drift from the depletion layer 55. Some of these photoelectrons 62 may drift to other pixels in relatively close proximity. Other photoelectrons 63 from the depletion region 55 will drift to the floating diffusion 30 and photoelectrons 64 will drift to the floating diffusion 30 from nearby pixels. All of these stray photoelectrons 62, 63, and 64 cause noise currents that interfere with the detection of the correct values of light intensity and cause distortion such as blooming and smearing of the image.
Active pixel sensor arrays may be operated in a read-reset mode with a row at a time being read out. This technique has minimum integration time to collect the photons and minimum time for generating a frame, however it may have motion artifacts due to non-simultaneous exposure.
A second type of operation of a CMOS active pixel sensor array is a block access mode. A block of pixels adjacent pixels are readout. This too has minimum integration time for a full block read out. Control for this type of read out is complicated
Typically, a CMOS active pixel sensor array is operated in a rolling shutter mode in which each row of the array is exposed at different instants of time. The non-simultaneous exposure of the pixels can lead to image distortion, for example, when there is relative motion between the imager and the image that is to be captured. Furthermore, although the exposure time generally is defined by the duration for which the photogate is turned on, floating diffusion regions can continue to collect photoelectrons even after the photogate is turned off. Transfer of such unwanted charges into the sense node can result in image distortion and excess noise. Furthermore, the distortions tend to become more pronounced as the exposure time is reduced.
An alternative to the rolling shutter mode of operation is the snapshot mode with single simultaneous conversion of the photons to the photoelectrons and transfer of the photoelectrons to the floating diffusion storage node. Each pixel is read out one at-a-time readout. Since all pixels are exposed essentially simultaneously, the motion artifact is minimized. However, relatively long integration times (10 msec) precludes the capture of high velocity moving objects without blurring or the motion artifact.
“A Snap-Shot CMOS Active Pixel Imager for Low-Noise, High-Speed Imaging”, Yang, et al., Technical Digest., International Electron Devices Meeting, December 1998, pp.: 45-48, presents the design and performance of a 128×128 snap-shot imager implemented in a standard single-poly CMOS technology. The pixel design and clocking scheme allows the imager to provide high-quality images without motion artifacts at high shutter speeds (<75 μsec, exposure), with low noise (<5 e−), immeasurable image lag, and excellent blooming protection.
“CMOS Difference Imagers with Charge-Leakage Compensation and Sum Output”, Seshadri, et al., IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, June 2001, pp. 125 128, 2001, and “CMOS Imager with Charge-Leakage Compensated Frame Difference and Sum Output”, Pain, et al., The 2001 IEEE International Symposium on Circuits and Systems, May 2001, Vol. 5, pp.: 223-226 present a new technique for implementing a low-power CMOS imager with simultaneous on-chip computation of the difference and sum of two successive frames. The imager uses an unbalanced differential signal chain to provide 17 fold reduction in leakage error in the frame-difference output.
“CMOS Image Sensor with NMOS-Only Global Shutter and Enhanced Responsivity”, Wany, et al., IEEE Transactions on Electron Devices, January 2003, Vol. 50, Issue: 1, pp.: 57-62, presents an NMOS-only pixel with a global shutter and subthreshold operation of the NMOS sample-and-hold transistor to increase optical responsivity by a factor of five to nine μV/photon, including fill factor. Wany et al further describes use of separate wells in the pixel to isolate the storage node from the photodiode showed good shutter efficiency.
U.S. Pat. No. 6,885,047 (Shinohara, et al.) describes a solid-state image sensing device. Each pixel of the image sensing device has a photodiode, a first transistor, and a second transistor. A potential barrier is provided under the drain region of the first transistor and the source region and/or the drain region of the second transistor.
U.S. Pat. No. 6,839,452 (Yang, et al.) teaches a dynamically re-configurable CMOS imagers for an active vision system. The CMOS imager includes a pixel array, at least one multi-resolution window operation circuit, and a pixel averaging circuit. The pixel array has an array of pixels configured to receive light signals from an image having at least one tracking target. The multi-resolution window operation circuits are configured to process the image. Each of the multi-resolution window operation circuits processes each tracking target within a particular multi-resolution window. The pixel averaging circuit is configured to sample and average pixels within the particular multi-resolution window.
U.S. Pat. No. 6,737,626 (Bidermann, et al.) teaches an integrated image sensor having a conditioned top silicon oxide layer and/or one or more additional insulating layers/structures to reduce optical and/or electrical noise. The image sensor has one or more insulating structures formed on the substrate and configured to inhibit the flow of electricity between a photoelement and its associated circuitry and/or the pixel and an adjacent pixel in the array.
U.S. Pat. No. 6,521,920 (Abe) provides a solid state image sensor with a primary first-conductivity-type semiconductor region which serves as a charge storage region of a photo-sensing area and a secondary first-conductivity-type semiconductor region for enlarging a charge collecting region of the photo-sensing area.
U.S. Pat. No. 6,403,998 (Inoue) describes solid-state image sensor having a first P-well area is provided in a surface portion of an n type silicon substrate and a second P-well area is selectively provided in the surface portion of the first P-well area. The second P-well area is higher in p type impurity concentration than the first P-well area. The photoelectric conversion section is formed in the first P-well area and the signal scanning circuit section is formed in the second P-well area.
U.S. Pat. No. 6,326,230 (Pain, et al.) describes high speed CMOS imager with motion artifact supression and anti-blooming. Each pixel of the CMOS imager includes a photoactive region in the semiconductor substrate, a sense node, and a power supply node. A transfer gate is disposed above the surface of the semiconductor substrate. A bias signal applied to the transfer gate sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node for transfer of photoelectrons to the sense node. A reset gate is disposed near the surface of the semiconductor substrate between the photoactive region and the power supply node. A reset signal on the reset gate sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node for clearing the photoelectrons from the photoactive region after read out of the electrical signal of an image without passing through the sense node.
U.S. Pat. No. 6,218,691 (Chung, et al.) presents a unit pixel array having a plurality of unit pixels formed on an N-type buried layer placed on a semiconductor substrate to isolate the unit pixel from the P-type epitaxial layer of a peripheral circuit.